GPS signal simulator designe

The GPS signal simulator that was designed consists of 3 major subsystems.
The three major subsystems are the PC and included software, FPGA board, and the analog, or
RF subsystem, which includes everything from the D/A converter up to the receiver. The PC
subsystem uses a chain of programs that are controlled by a graphical user interface. These
programs take in data such as the receiver’s starting location and trajectory, as well as a number
of parameters and special files that are needed to calculate the desired information. The end
result of the PC subsystem is a set of data that can be transmitted to the FPGA board. This data
includes line-of-sight code phase, satellite ID number, and signal amplitude level for each of four
satellites that are in view of the receiver.
The FPGA subsystem communicates with the PC and uses the received data to index lookup
tables which then provide values for the C/A code and carrier signals for each sample. The C/A
code is a unique sequence of 1023 bits, or “chips,” that is generated by each satellite. This
sequence repeats every 1ms on each satellite, and it is used in GPS receivers to lock on to the
GPS signal and obtain a position measurement in some cases. Since the sampling rate is much
higher than the communication update rate, the FPGA performs a great deal of linear
interpolation on the received data in order to calculate the current values at each sample point.
The calculations for each satellite in view are done in parallel so that the entire operation can
happen in one clock cycle for each sample.