Global Positioning System

RF subsystem

The RF subsystem is the section of the design that actually generates the signals needed to drive
the receiver. The D/A converter takes sample data from the FPGA at 8.184 MHz and generates
an approximation of the analog signal. This signal, after being converted from differential to
single-ended, is then sent to a mixer to mix the signal up to the GPS L1 frequency of 1575.42
MHz. The resulting signal power is too high for a GPS receiver to recognize, so a series of
attenuators is used to lower the signal power. The signal is then routed to the receiver for testing.
The first major area of focus was the PC subsystem. This is the software portion of the project
which runs on a PC with Windows XP and a parallel port. The main function of the subsystem is
to allow the user to provide the simulation inputs. The subsystem then performs a number of
calculations and formats the data to be sent to the FPGA.
A screenshot of the GUI application can be seen in Figure 2. This screen allows the user to
select and enter all of the necessary inputs. These include a trajectory file, almanac file, antenna
file, starting location, and starting date/time. The trajectory file describes the movement of the
receiver antenna from the starting location, specified in durations of jerk along the axes of yaw,
pitch, roll, and thrust. The initial acceleration, velocity, and attitude are assumed to be zero. The
almanac file is in the industry standard RINEX2 format, containing ephemeris data for each
satellite. The antenna file models the receiver antenna, containing values for the antenna gain
through the ranges of azimuth and elevation angles. This file can also be used to model antenna
blockage from certain directions.
Once the user has made these selections, he or she can begin the pre-processing and simulation
process. During pre-processing, a series of calculations are performed and the data to be sent to
the FPGA is the end result. The simulation process then becomes simply transmitting this data
to the FPGA sequentially.

This website was created for free with Own-Free-Website.com. Would you also like to have your own website?
Sign up for free